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1 S2202 dual gigabit ethernet device october 9, 2000 / revision c S2202 ? dual gigabit ethernet device device specification mac (asic) s2002 dual gigabit ethernet interface mac (asic) to serial backplane S2202 ge interface serial bp driver figure 1. typical dual gigabit ethernet application features ? 1250 mhz (gigabit ethernet) operating rate - half rate operation ? ieee 802.3z gigabit ethernet compatible ? dual transmitter with phase-locked loop (pll) clock synthesis from low speed reference ? dual receiver pll provides clock and data recovery ? internally series terminated ttl outputs ? low-jitter serial pecl interface ? individual local loopback control ? jtag 1149.1 boundary scan on low speed i/o signals ? interfaces with coax, twinax, or fiber optics ? single +3.3v supply, 1.85 w power dissipation ? compact 21mm x 21mm 156 tbga package applications ? ethernet backbones ? workstation ? frame buffer ? switched networks ? data broadcast environments ? proprietary extended backplanes general description the S2202 facilitates high-speed serial transmission of data in a variety of applications including gigabit ethernet, serial backplanes, and proprietary point to point links. the chip provides two separate trans- ceivers which are operated individually for a data capacity of >2 gbps. each bi-directional channel provides parallel-to-se- rial and serial-to-parallel conversion, clock genera- tion/recovery, and framing. the on-chip transmit pll synthesizes the high-speed clock from a low-speed reference. the on-chip dual receive pll is used for clock recovery and data re-timing on the two inde- pendent data inputs. the transmitter and receiver each support differential pecl-compatible i/o for copper or fiber optic component interfaces with ex- cellent signal integrity. local loopback mode allows for system diagnostics. the chip requires a 3.3v power supply and dissipates 1.85 watts. figure 1 shows the S2202 and s2002 in a gigabit ethernet application. figure 2 summarizes the in- put/output signals of the device. figures 3 and 4 show the transmit and receive block diagrams, re- spectively.
2 dual gigabit ethernet device S2202 october 9, 2000 / revision c figure 2. S2202 input/output diagram refclk rate reset txap/n txbp/n rxap/n rxbp/n dina[0:9] 10 dinb[0:9] 10 tbca tbcb 10 rbc1/0a 10 rbc1/0b douta[0:9] doutb[0:9] clksel tmode tclko com_deta com_detb testmode2 cmode testmode1 testmode lpena lpenb trs tms tck tdi tdo
3 S2202 dual gigabit ethernet device october 9, 2000 / revision c figure 3. transmitter block diagram 10 dina[0:9] tmode 10 shift reg 10 dinb[0:9] 10 shift reg din pll 10x/20x refclk clksel rate refclk tclko fifo (input) fifo (input) tbca tbcb txap txan txabp txbp txbn txbbp 01 01 tmode
4 dual gigabit ethernet device S2202 october 9, 2000 / revision c figure 4. receiver block diagram dout cru serial- parallel dout cru serial- parallel com_deta rbc1/0a douta[0:9] rxap rxan lpena rxbp rxbn lpenb com_detb doutb[0:9] q fifo (output) txbbp txabp refclk 10 10 rbc1/0b cmode rate fifo (output) 10 2 2 10 tmode
5 S2202 dual gigabit ethernet device october 9, 2000 / revision c transmitter description the transmitter section of the S2202 contains a single pll which is used to generate the serial rate transmit clock for all transmitters. two channels are provided with a variety of options regarding input clocking and loopback. the transmitters operate at 1.250 ghz, 10 or 20 times the reference clock frequency. data input the S2202 has been designed to simplify the paral- lel interface data transfer and provides the utmost in flexibility regarding clocking of parallel data. the S2202 incorporates a unique fifo structure on both the parallel inputs and the parallel outputs which en- ables the user to provide a clean reference source for the pll and to accept a separate external clock which is used exclusively to reliably clock data into the device. data can also be clocked in using the refclk. data is input to each channel of the S2202 nominally as a 10 bit wide word. an input fifo and a clock input, tbcx, are provided for each channel of the S2202. the device can operate in two different modes. the S2202 can be configured to use either the tclkx (tclk mode) input or the refclk input (refclk mode). in tclk or refclk mode, 10 bits of data are clocked into its fifo with the tbcx provided with each 10 bits. table 1 provides a sum- mary of the input modes of the S2202. operation in the tbc mode makes it easier for us- ers to meet the relatively narrow setup and hold time window required by the 125 mbps 10-bit interface. the tbc signal is used to clock the data into an internal holding register and the S2202 synchronizes its internal data flow to ensure stable operation. however, regardless of the clock mode, refclk is always the vco reference clock. this facilitates the provision of a clean reference clock resulting in mini- mum jitter on the serial output. the tbc must be frequency locked to refclk, but may have an arbi- trary phase relationship. adjustment of internal tim- ing of the S2202 is performed during reset. once synchronized, the user must ensure that the timing of the tbc signal does not change by more than 3 ns relative to the refclk. figure 5 demonstrates the flexibility afforded by the S2202. a low jitter reference is provided directly to the S2202 at either 1/10 or 1/20 the serial data rate. this ensures minimum jitter in the synthesized clock used for serial data transmission. a system clock output at the parallel word rate, tclko, is derived from the pll and provided to the upstream circuit as a system clock. the frequency of this output is con- stant at the parallel word rate, 1/10 the serial data rate, regardless of whether the reference is provided at 1/10 or 1/20 the serial data rate. this clock can be buffered as required without concern about added delay. there is no phase requirement between tclko and tbcx, which is provided back to the S2202, other than that they remain within 3ns of the phase relationship established at reset. the S2202 also supports the traditional refclk clocking found in many gigabit ethernet applications and is illustrated in figure 6. half rate operation the S2202 supports full and half rate operation for all modes of operation. when rate is low, the S2202 serial data rate equals the vco frequency. when rate is high, the vco is divided by 2 before being provided to the chip. thus the S2202 can sup- port gigabit ethernet and serial backplane functions at both full and half the vco rate. see table 3. parallel to serial conversion the 10-bit parallel data handled by the S2202 device should be from a dc-balanced encoding scheme, such as the 8b/10b transmission code, in which in- formation to be transmitted is encoded, 8 bits at a time, into a 10-bit transmission character and must be compliant with ieee 802.3z gigabit ethernet. the 8b/10b transmission code includes serial en- coding and decoding rules, special characters, and error control. information is encoded, 8 bits at a time, into a 10 bit transmission character. the characters defined by this code ensure that short run lengths and enough transitions are present in the serial bit stream to make clock recovery possible at the re- ceiver. the encoding also greatly increases the like- lihood of detecting any single or multiple errors that might occur during the transmission and reception of data 1 . 1. a.x. widner and p.a. franaszek, "a byte-oriented dc bal- anced (0,4) 8b/10b transmission code," ibm research report rc9391, may 1982. table 1. input modes e d o m tn o i t a r e p o 0 a t a d k c o l c o t d e s u k l c f e r . e d o m k l c f e r . s l e n n a h c l l a r o f s o f i f o t n i 1 s o f i f o t n i a t a d k c o l c o t d e s u x c b t . e d o m c b t . s l e n n a h c l l a r o f note that internal synchronization of fifos is performed upon de-assertion of reset.
6 dual gigabit ethernet device S2202 october 9, 2000 / revision c table 2. data to 8b/10b alphabetic representation table 3. operating rates e t a rl e s k l c k l c f e r y c n e u q e r f l a i r e s e t a r t u p t u o o k l c t y c n e u q e r f 00 z h m 5 2 1z h m 0 5 2 1z h m 5 2 1 01 z h m 5 . 2 6z h m 0 5 2 1z h m 5 2 1 10 z h m 5 . 2 6z h m 5 2 6z h m 5 . 2 6 11 z h m 5 2 . 1 3z h m 5 2 6z h m 5 . 2 6 . figure 5. din data clocking with tbc refclk S2202 125 mhz or 62.5 mhz tbcx dinx[0:9] ref oscillator mac asic tclko pll e t y b a t a d ] 9 : 0 [ t u o d r o ] 9 : 0 [ n i d 0123456789 c i r e m u n a h p l a b 0 1 / b 8 n o i t a t n e s e r p e r abcdei fghj table 2 identifies the mapping of the 8b/10b charac- ters to the data inputs of the S2202. the S2202 will serialize the parallel data for each channel and will transmit bit a or din[0] first. frequency synthesizer (pll) the S2202 synthesizes a serial transmit clock from the reference signal. upon startup, the S2202 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock in- puts. reliable locking of the transmit pll is assured, but a lock-detect output is not provided. reference clock input the reference clock input must be supplied with a low-jitter clock source. all reference clocks in a sys- tem must be within 200 ppm of each other to ensure that the clock recovery units can lock to the serial data. gigabit ethernet applications may require tighter tolerances. the frequency of the reference clock must be either 1/10 the serial data rate, clksel = 0, or 1/20 the serial data rate, clksel=1. in both cases the fre- quency of the parallel word rate output, tclko, is constant at 1/10 the serial data rate. see table 3. serial data outputs the S2202 provides lvpecl level serial outputs. the serial outputs do not require output pulldown resistors. outputs are designed to perform optimally when ac-coupled. transmit fifo initialization the transmit fifo must be initialized after stable delivery of data and tbc to the parallel interface, and before entering the normal operational state of the circuit. fifo initialization is performed upon the de-assertion of the reset signal. tclko will oper- ate normally regardless of the state of reset. figure 6. ge din clocking with refclk refclk S2202 tbcx dinx[0:9] ref oscillator mac asic tclko pll 125 mhz
7 S2202 dual gigabit ethernet device october 9, 2000 / revision c receiver description each receiver channel is designed to implement a serial backplane receiver function through the physi- cal layer. a block diagram showing the basic func- tion is provided in figure 4. whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. after acquiring bit synchronization, the S2202 searches the serial bit stream for the occur- rence of a k28.5 character on which to perform word synchronization. once synchronization on both bit and word boundaries is achieved, the receiver pro- vides the word-aligned data on its parallel outputs. data input a differential input receiver is provided for each chan- nel of the S2202. each channel has a loopback mode in which the serial data from the transmitter replaces external serial data. the loopback function for each channel is enabled by its respective lpen input. the high speed serial inputs to the S2202 are inter- nally biased to vdd-1.3v. all that is required exter- nally are ac-coupling and line-to-line differential termination. clock recovery function clock recovery is performed on the input data stream for each channel of the S2202. the receiver pll has been optimized for the anticipated needs of serial backplane systems. a simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. the decision is based upon the frequency and run length of the serial data inputs. if at any time the frequency or run length checks are violated, the state machine forces the vco to lock to the refer- ence clock. this allows the vco to maintain the cor- rect frequency in the absence of data. the lock to reference frequency criteria ensure that the S2202 will respond to variations in the serial data input frequency (compared to the reference fre- quency). the new lock state is dependent upon the current lock state, as shown in table 4. the run-length criteria ensure that the S2202 will respond appropriately and quickly to a loss of signal. the run-length checker flags a condition of consecu- tive ones or zeros across 12 parallel words. thus 119 or less consecutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120C128 may or may not, depending on how the data aligns across byte boundaries. if both the off-frequency detect circuitry test and the run-length test are satisfied, the cru will attempt to lock to the incoming data. it is possible for the run length test to be satisfied due to noise on the inputs, even if no signal is present. in this case the receiver vco will maintain frequency accuracy to within 100 ppm of the target rate as determined by refclk. in any transfer of pll control from the serial data to the reference clock, the rbc1/0x outputs remain phase continuous and glitch free, assuring the integ- rity of downstream clocking. reference clock input a single reference clock, which serves both transmit- ter and receiver, must be provided from a low jitter clock source. the frequency of the received data stream (divided-by -10 or -20) must be within 200 ppm of the reference clock to ensure reliable locking of the receiver pll. serial-to-parallel conversion once bit synchronization has been attained by the S2202 cru, the S2202 must synchronize to the 10 bit word boundary. word synchronization in the S2202 is accomplished by detecting and aligning to the 8b/10b k28.5 codeword. the S2202 will detect and byte-align to either polarity of the k28.5. each channel of the S2202 will detect and align to a k28.5 anywhere in the data stream. for tclk or refclk mode operation, the presence of a k28.5 is indicated for each channel by the assertion of the com_detx signal. k c o l t n e r r u c e t a t se t a t s e t a t s e t a t se t a t s y c n e u q e r f l l p ) k l c f e r . s v () k l c f e r . s v ( ) k l c f e r . s v ( ) k l c f e r . s v () k l c f e r . s v ( e t a t s k c o l w e n d e k c o l m p p 8 8 4 d e k c o l n u d e k c o l n u m p p 4 4 2 d e k c o l n u table 4. lock to reference frequency criteria
8 dual gigabit ethernet device S2202 october 9, 2000 / revision c data output data is output on the dout[ 0:9] outputs. the com_det signal is used to indicate the reception of a valid k28.5 character. the S2202 ttl outputs are optimized to drive 65 w line impedances. internal source matching provides good performance on unterminated lines of reason- able length. parallel output clock rate two output clock modes are supported, as shown in table 5. when cmode is high, a complementary ttl clock at the data rate is provided on the rbc1/ 0x outputs. data should be clocked on the rising edge of rbc1x. when cmode is low, a comple- mentary ttl clock at half the data rate is provided. data should be latched on the rising edge of rbc1x and the rising edge of rbc0x. e d o me d o m cq e r f x 0 / 1 c b r e d o m k c o l c f l a h0z h m 5 . 2 6 e d o m k c o l c l l u f1z h m 5 2 1 table 5. output clock mode in gigabit ethernet applications, multiple consecu- tive k28.5 characters cannot be generated. how- ever, for serial backplane applications this can occur. the S2202 must be able to operate properly when multiple k28.5 characters are received. after the first k28.5 is detected and aligned, the rbc1/0x clock will operate without glitches or loss of cycles. receiver output clocking the S2202 parallel output clock source is deter- mined by the tmode selection. when refclk clocking is selected (tmode = low), the parallel output clocks (rcxp/n) are sourced from the tclka input. when tclk clocking is selected (external clocking mode), the parallel output clocks are de- rived from the recovered clock from each channel. table 5a describes the receiver output clocking op- tions available. e d o m t k c o l c t u p n i e c r u o s k c o l c t u p t u o e c r u o s 0k l c f e ra c b t 1x c b tx c b r table 5a. S2202 data clocking when tclka is the output clock source, refclk and tclka must equal the parallel word rate (clksel = low). additionally, the recovered clocks and the clock input on tclka must be frequency locked in order to avoid overflow/underflow of the internal fifos. the propagation delay between tclka and doutx, listed in table 21, shows that the phase delay between tclka and the rcxp/n outputs may vary more than a bit time based on process variation. the recommended clocking configuration for exter- nal clocking mode (refclk input clocking) is shown in figure 7. tclka is sourced from tclko, which is frequency locked to the reference clock input. refclk serdes tclka ref oscillator controller/mac asic/fpga tclko pll parallel data rcxp/n 2 recovered clock figure 7. external receiver clocking
9 S2202 dual gigabit ethernet device october 9, 2000 / revision c figure 8. S2202 diagnostic loopback operation cru csu other operating modes operating frequency rate the S2202 is designed to operate at the gigabit ethernet rate of 1.250 ghz. loopback mode when loopback mode is enabled, the serial data from the transmitter is provided to the serial input of the receiver, as shown in figure 8. this provides the ability to perform system diagnostics and off-line testing of the interface to verify the integrity of the serial channel. loopback mode is enabled indepen- dently for each channel using its respective loopback-enable input, lpen. test modes the reset pin is used to initialize the transmit fifos and must be asserted (low) prior to entering the normal operational state (see section transmit fifo initialization). note: serial output data remains active during loopback opera- tion to enable other system tests to be performed. jtag testing the jtag implementation for the S2202 is compli- ant with the ieee1149.1 requirements. jtag is used to test the connectivity of the pins on the chip. the tap, (test access port), provides access to the test logic of the chip. when trst is asserted the tap is initialized. tap is a state machine that is controlled by tms. the test instruction and data are loaded through tdi on the rising edge of tck. when tms is high the test instruction is loaded into the instruction register. when tms is low the test data is loaded into the data register. tdo changes on the falling edge of tck. all input pins, including clocks, that have boundary scan are observe only. they can be sampled in either normal operational or test mode. all output pins that have boundary scan, are observe and control. they can be sampled as they are driven out of the chip in normal operational mode, and they can be driven out of the chip in test mode using the extest instruction. since jtag testing operates only on digital signals there are some pins with analog signals that jtag does not cover. the jtag imple- mentation has the three required instruction, bypass, extest, and sample/preload. instruction code bypass 11 extest 00 sample/preload 01 id code 10 jtag instruction description: the bypass register contains a single shift-register stage and is used to provide a minimum-length serial path between the tdi and tdo pins of a component when no test operation of that component is re- quired. this allows more rapid movement of test data to and from other components on a board that are required to perform test operations. the extest instruction allows testing of off-chip cir- cuitry and board level interconnections. data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register stages using the sample/preload instruction prior to selection of the extest instruction. the sample/preload instruction allows a snap- shot of the normal operation of the component to be taken and examined. it also allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register prior to selection of the other boundary-scan test instructions. the following table provides a list of the pins that are jtag tested. each port has a boundary scan regis- ter (bsr), unless otherwise noted. the following fea- tures are described: the jtag mode of each register (input, output2, or internal (refers to an internal pack- age pin)), the direction of the port if it has a bound- ary scan register (in or out), and the position of this register on the scan chain.
10 dual gigabit ethernet device S2202 october 9, 2000 / revision c table 6. jtag pin assignments 2 0 2 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i 2 e d o m t s e t2 _ e d o m t s e tt u p n i0- e d o m ce d o m ct u p n i1- e d o m t s e t0 _ e d o m t s e tt u p n i2- l a n r e t n i3- b n e p lb n e p lt u p n i4- l a n r e t n i5- a n e p la n e p lt u p n i6- l e s k l cl e s k l ct u p n i7- e d o m te d o m tt u p n i8- l a n r e t n i9- t e s e rt e s e rt u p n i0 1- k l c f e rk l c f e rt u p n i1 1- o k l c t _ k l c _ t i m s n a r t t u o _ f u b 2 t u p t u o-2 1 l a n r e t n i2 2 - 3 1- 1 e d o m t s e t1 _ e d o m t s e tt u p n i3 2- 9 b n i d) 9 ( b _ n i a t a d tt u p n i4 2- 8 b n i d) 8 ( b _ n i a t a d tt u p n i5 2- 7 b n i d) 7 ( b _ n i a t a d tt u p n i6 2- 6 b n i d) 6 ( b _ n i a t a d tt u p n i7 2- 5 b n i d) 5 ( b _ n i a t a d tt u p n i8 2- 4 b n i d) 4 ( b _ n i a t a d tt u p n i9 2- 3 b n i d) 3 ( b _ n i a t a d tt u p n i0 3- 2 b n i d) 2 ( b _ n i a t a d tt u p n i1 3- 1 b n i d) 1 ( b _ n i a t a d tt u p n i2 3- 0 b n i d) 0 ( b _ n i a t a d tt u p n i3 3- b c b tb k l c tt u p n i4 3- l a n r e t n i5 4 - 5 3- 9 a n i d) 9 ( a _ n i a t a d tt u p n i6 4- 8 a n i d) 8 ( a _ n i a t a d tt u p n i7 4- 7 a n i d) 7 ( a _ n i a t a d tt u p n i8 4- 6 a n i d) 6 ( a _ n i a t a d tt u p n i9 4- 5 a n i d) 5 ( a _ n i a t a d tt u p n i0 5- 4 a n i d) 4 ( a _ n i a t a d tt u p n i1 5- 3 a n i d) 3 ( a _ n i a t a d tt u p n i2 5- 2 a n i d) 2 ( a _ n i a t a d tt u p n i3 5- 1 a n i d) 1 ( a _ n i a t a d tt u p n i4 5- 0 a n i d) 0 ( a _ n i a t a d tt u p n i5 5- a c b ta k l c tt u p n i6 5- l a n r e t n i-9 6 - 7 5 b 1 c b rp b c r2 t u p t u o-0 7 b 0 c b rn b c r2 t u p t u o-1 7 7 b t u o d) 7 ( b _ t u o a t a d r2 t u p t u o-2 7 6 b t u o d) 6 ( b _ t u o a t a d r2 t u p t u o-3 7 5 b t u o d) 5 ( b _ t u o a t a d r2 t u p t u o-4 7 4 b t u o d) 4 ( b _ t u o a t a d r2 t u p t u o-5 7 3 b t u o d) 3 ( b _ t u o a t a d r2 t u p t u o-6 7 2 0 2 2 s e m a n n i p n a c s _ e r o c e m a n t r o p g a t j e d o m g n i t u o r t u o n i 2 b t u o d) 2 ( b _ t u o a t a d r2 t u p t u o-7 7 1 b t u o d) 1 ( b _ t u o a t a d r2 t u p t u o-8 7 0 b t u o d) 0 ( b _ t u o a t a d r2 t u p t u o-9 7 9 b t u o d) 9 ( b _ t u o a t a d r2 t u p t u o-0 8 b t e d _ m o cb _ d f o e2 t u p t u o-1 8 8 b t u o d) 8 ( b _ t u o a t a d r2 t u p t u o-2 8 l a n r e t n i-5 9 - 3 8 a 1 c b rp a c r2 t u p t u o-6 9 a 0 c b rn a c r2 t u p t u o-7 9 9 a t u o d) 9 ( a _ t u o a t a d r2 t u p t u o-8 9 7 a t u o d) 7 ( a _ t u o a t a d r2 t u p t u o-9 9 6 a t u o d) 6 ( a _ t u o a t a d r2 t u p t u o-0 0 1 5 a t u o d) 5 ( a _ t u o a t a d r2 t u p t u o-1 0 1 4 a t u o d) 4 ( a _ t u o a t a d r2 t u p t u o-2 0 1 3 a t u o d) 3 ( a _ t u o a t a d r2 t u p t u o-3 0 1 2 a t u o d) 2 ( a _ t u o a t a d r2 t u p t u o-4 0 1 1 a t u o d) 1 ( a _ t u o a t a d r2 t u p t u o-5 0 1 0 a t u o d) 0 ( a _ t u o a t a d r2 t u p t u o-6 0 1 a t e d _ m o ca _ d f o e2 t u p t u o-7 0 1 8 a t u o d) 8 ( a _ t u o a t a d r2 t u p t u o-8 0 1 l a n r e t n i-9 0 1 s n i p l o r t n o c g a t j ) r e t s i g e r n a c s y r a d n u o b a e v a h t o n o d t a h t s t r o p ( k c tk c t _ g a t j--- i d ti d t _ g a t j--- o d to d t _ g a t j--- s m ts m t _ g a t j--- s r ts r t _ g a t j--- d e t s e t g a t j t o n s n i p p a x t---- n a x t---- p b x t---- n b x t---- e t a r---- p a x r---- n a x r---- p b x r---- n b x r----
11 S2202 dual gigabit ethernet device october 9, 2000 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 9 a n i d 8 a n i d 7 a n i d 6 a n i d 5 a n i d 4 a n i d 3 a n i d 2 a n i d 1 a n i d 0 a n i d l t ti 5 1 t 3 1 r 2 1 p 4 1 t 2 1 r 1 1 p 3 1 t 1 1 r 2 1 t 0 1 p d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . a l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o a c b t f o e g d e g n i s i r e h t n o n i a c b tl t ti 0 1 rd e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . a k c o l c e t y b t i m s n a r t , w o l s i e d o m t n e h w . 2 0 2 2 s e h t o t n i ] 9 : 0 [ a n i d n o a t a d k c o l c o t . d e r o n g i s i a c b t 9 b n i d 8 b n i d 7 b n i d 6 b n i d 5 b n i d 4 b n i d 3 b n i d 2 b n i d 1 b n i d 0 b n i d l t ti 4 1 l 6 1 m 5 1 m 4 1 m 6 1 n 5 1 n 4 1 n 6 1 p 5 1 p 6 1 r n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . b l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o b c b t f o e g d e g n i s i r e h t n o b c b tl t ti 4 1 pd e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . b k c o l c e t y b t i m s n a r t , w o l s i e d o m t n e h w . 2 0 2 2 s e h t o t n i ] 9 : 0 [ b n i d n o a t a d k c o l c o t . d e r o n g i s i b c b t table 7. transmitter input pin assignment and descriptions
12 dual gigabit ethernet device S2202 october 9, 2000 / revision c table 9. mode control signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d e d o m t s e tl t ti3 d. n o i t a r e p o l a m r o n r o f w o l p e e k . l o r t n o c e d o m t s e t 1 e d o m t s e tl t ti 5 1 l. n o i t a r e p o l a m r o n r o f w o l p e e k . l o r t n o c e d o m t s e t 2 e d o m t s e tl t ti4 c. n o i t a r e p o l a m r o n r o f w o l p e e k . l o r t n o c e d o m t s e t e d o m tl t ti 3 1 ao t d e s u k c o l c e h t f o e c r u o s e h t s l o r t n o c . l o r t n o c e d o m r e f s n a r t s i e d o m t n e h w . 2 0 2 2 s e h t m o r f d n a o t a t a d t u p t u o d n a t u p n i . 2 0 2 2 s e h t o t n i ] 9 : 0 [ x n i d n o a t a d k c o l c o t d e s u s i k l c f e r , w o l e h t f o t u o ] 9 : 0 [ x t u o d a t a d l e l l a r a p k c o l c o t d e s u s i a c b t o t d e s u e r a s t u p n i x c b t e h t , h g i h s i e d o m t n e h w . e c i v e d e r a s k c o l c t u p t u o e h t . s l e n n a h c e v i t c e p s e r r i e h t o t n i a t a d k c o l c . s u r c ' s r e v i e c e r e h t m o r f d e v i r e d l e s k l cl t ti 1 1 be h t r o f l l p e h t s e r u g i f n o c l a n g i s s i h t . t u p n i t c e l e s k l c f e r k l c f e r e h t , 0 = l e s k l c n e h w . y c n e u q e r f k l c f e r e t a i r p o r p p a e h t , 1 = l e s k l c n e h w . e t a r d r o w l e l l a r a p e h t s l a u q e y c n e u q e r f . e t a r a t a d l e l l a r a p e h t f l a h s i y c n e u q e r f k l c f e r k l c f e rl t ti 4 1 jy c n e u q e r f d n a o c v t i m s n a r t e h t r o f d e s u s i k c o l c e c n e r e f e r . a t a d l a i r e s r e v i e c e r e h t m o r f d e r e v o c e r k c o l c e h t r o f k c e h c t e s e rl t ti 5 1 bd e c r o f s i l l p r e v i e c e r e h t . t e s e r n i d l e h s i 2 0 2 2 s e h t , w o l n e h w e g d e g n i s i r e h t n o d e z i l a i t i n i e r a s o f i f e h t . k l c f e r e h t o t k c o l o t . y l l a m r o n s e t a r e p o 2 0 2 2 s e h t , h g i h n e h w . t e s e r f o e t a rl t ti 1 1 cl a u q e e t a r t u p t u o l a i r e s e h t h t i w s e t a r e p o 2 0 2 2 s e h t , w o l n e h w e h t h t i w s e t a r e p o 2 0 2 2 s e h t , h g i h n e h w . y c n e u q e r f o c v e h t o t . s n o i t c n u f l l a r o f 2 y b d e d i v i d y l l a n r e t n i o c v note: all ttl inputs except refclk have internal pull-up networks. table 8. transmitter output signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x t n a x t . f f i d l c e p v l o6 1 d 6 1 e . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h p b x t n b x t . f f i d l c e p v l o6 1 g 6 1 f . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h o k l c tl t to 5 1 kd e d i v o r p s i k c o l c s i h t . e t a r a t a d l e l l a r a p e h t t a k c o l c t u p t u o l t t . y r t i u c r i c m a e r t s - p u y b e s u r o f
13 S2202 dual gigabit ethernet device october 9, 2000 / revision c table 10. receiver output pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 9 a t u o d 8 a t u o d 7 a t u o d 6 a t u o d 5 a t u o d 4 a t u o d 3 a t u o d 2 a t u o d 1 a t u o d 0 a t u o d l t to2 j 2 g 2 l 1 l 2 k 1 k 3 j 1 j 3 h 2 h d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r a l e n n a h c e h t n o d i l a v d n a e d o m k c o l c l l u f n i a 1 c b r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i a 0 c b r d n a a 1 c b r h t o b f o e g d e g n i s i r a t e d _ m o cl t to1 ga t a h t s e t a c i d n i t u p t u o s i h t n o h g i h a . t c e t e d a m m o c a l e n n a h c a t a d l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v . ] 9 : 0 [ a t u o d s t u p t u o a 1 c b r a 0 c b r l t to1 m 3 l d n a ] 9 : 0 [ a t u o d , a t a d e v i e c e r l e l l a r a p . s k c o l c e t y b e v i e c e r l l u f n i n e h w a 1 c b r f o e g d e g n i s i r e h t n o d i l a v e r a a t e d _ m o c d n a a 1 c b r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c . e d o m k c o l c f l a h n i a 0 c b r 9 b t u o d 8 b t u o d 7 b t u o d 6 b t u o d 5 b t u o d 4 b t u o d 3 b t u o d 2 b t u o d 1 b t u o d 0 b t u o d l t to4 p 2 p 8 p 5 t 6 r 6 p 5 r 3 t 5 p 3 r d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r b l e n n a h c e h t n o d i l a v d n a e d o m k c o l c l l u f n i b 1 c b r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i b 0 c b r d n a b 1 c b r h t o b f o e g d e g n i s i r b t e d _ m o cl t to3 pa t a h t s e t a c i d n i t u p t u o s i h t n o h g i h a . t c e t e d a m m o c b l e n n a h c a t a d l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v . ] 9 : 0 [ b t u o d s t u p t u o b 1 c b r b 0 c b r l t to7 r 7 p d n a ] 9 : 0 [ b t u o d , a t a d e v i e c e r l e l l a r a p . s k c o l c e t y b e v i e c e r l l u f n i n e h w b 1 c b r f o e g d e g n i s i r e h t n o d i l a v e r a b t e d _ m o c d n a b 1 c b r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c . e d o m k c o l c f l a h n i b 0 c b r
14 dual gigabit ethernet device S2202 october 9, 2000 / revision c table 13. power and ground signals table 11. receiver input pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a x r n a x r . f f i d l c e p v l i3 a 4 a e h t s i p a x r . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d d d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n a x r , t u p n i e v i t i s o p . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - p b x r n b x r . f f i d l c e p v l i8 a 9 a e h t s i p b x r . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d d d v o t d e s a i b y l l a n r e t n i . e v i t a g e n e h t s i n b x r , t u p n i e v i t i s o p . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - table 12. receiver control signals e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d a n e p l b n e p l l t ti 4 1 c 4 1 h l a i r e s d e e p s h g i h e h t s i e c r u o s t u p n i , w o l n e h w . e l b a n e k c a b p o o l h c a e r o f t u p t u o l a i r e s e h t , h g i h n e h w . l e n n a h c h c a e r o f t u p n i . t u p n i s t i o t k c a b d e p o o l s i l e n n a h c e d o m cl t ti2 cs k c o l c t u p t u o l e l l a r a p e h t , w o l n e h w . l o r t n o c e d o m k c o l c e h t , h g i h n e h w . e t a r a t a d e h t 2 / 1 o t l a u q e s i e t a r ) x 0 / 1 c b r ( . e t a r a t a d e h t o t l a u q e s i e t a r ) x 0 / 1 c b r ( s k c o l c t u p t u o l e l l a r a p note: all ttl inputs except refclk have internal pull-up networks. e m a n n i p. y t q# n i pn o i t p i r c s e d a d d v4, 4 b , 6 a 8 c , 3 1 b . e s i o n w o l ) d d v ( r e w o p g o l a n a a s s v3, 8 b , 2 a 3 1 c . ) s s v ( d n u o r g g o l a n a d d v3, 6 c , 2 1 b 9 c . ) d d v ( y r t i u c r i c d e e p s h g i h r o f r e w o p s s v b u s s s v 8, 1 1 a , 7 a , 4 1 a , 2 1 a , 7 b , 5 b 2 1 c , 7 c . ) s s v ( y r t i u c r i c d e e p s h g i h r o f d n u o r g
15 S2202 dual gigabit ethernet device october 9, 2000 / revision c e m a n n i p. y t q# n i pn o i t p i r c s e d r w p l c e p4, 5 1 f , 5 1 d 5 1 h , 4 1 g ) d d v ( r e w o p l c e p d n g l c e p26 1 c 6 1 j ) s s v ( d n u o r g l c e p r w p g i d6, 1 c , 2 b , 5 1 j , 2 d 9 p , 1 n ) d d v ( r e w o p y r t i u c r i c e r o c d n g g i d8, 1 d , 3 c , 3 e , 2 e , 1 r , 6 1 k 1 1 t , 1 t ) s s v ( d n u o r g y r t i u c r i c e r o c r w p l t t8, 3 g , 1 f , 2 m , 1 h , 4 r , 1 p 7 t , 8 r ) d d v ( o / i l t t r o f r e w o p d n g l t t0 1, 2 f , 1 e , 3 k , 3 f , 3 n , 3 m , 2 t , 2 r 8 t , 4 t ) s s v ( o / i l t t r o f d n u o r g r w p26 1 a 1 b r e w o p d n g5, 6 1 l , 4 1 k , 4 1 r , 3 1 p 6 1 t d n u o r g 1 p a c 2 p a c 25 1 a 4 1 b r o t i c a p a c r e t l i f p o o l l a n r e t x e r o f s n i p c n8 1, 5 a , 1 a , 9 b , 6 b , 5 c , 6 1 b , 5 1 c , 4 1 e , 4 1 d , 4 1 f , 5 1 e , 2 n , 5 1 g , 5 1 r , 9 r , 9 t , 6 t 0 1 t . t c e n n o c t o n o d . s n i p t s e t s a d e s u . d e t c e n n o c t o n table 13. power and ground signals (continued)
16 dual gigabit ethernet device S2202 october 9, 2000 / revision c e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d s m tl t ti0 1 a. e c i v e d f o g n i t s e t g a t j s e l b a n e . t c e l e s e d o m t s e t k c tl t ti0 1 b. k c o l c t s e t g a t j . k c o l c t s e t i d tl t ti0 1 c. t u p n i a t a d g a t j . n i a t a d t s e t o d tl t t o e t a t s i r t 6 1 h r e d n u e c n a d e p m i h g i h e b n a c . t u p t u o a t a d g a t j . t u o a t a d t s e t . d n a m m o c r e l l o r t n o c g a t j s r tl t ti3 b. e n i h c a m e t a t s t s e t g a t j s t e s e r . t e s e r t s e t table 14. jtag test signals
17 S2202 dual gigabit ethernet device october 9, 2000 / revision c figure 9. S2202 pinout (bottom view) a b c d e f g h j k l m n p r t 1 c nr w pr w p g i dd n g g i dd n g l t tr w p l t t _ m o c a t e d r w p l t t2 a t u o d4 a t u o d6 a t u o da 1 c b rr w p g i dr w p l t td n g g i dd n g g i d 2 a s s vr w p g i de d o m cr w p g i dd n g g i dd n g l t t8 a t u o d0 a t u o d9 a t u o d5 a t u o d7 a t u o dr w p l t tc n8 b t u o dd n g l t td n g l t t 3 p a x rs r td n g g i d t s e t e d o m d n g g i dd n g l t tr w p l t t1 a t u o d3 a t u o dd n g l t ta 0 c b rd n g l t td n g l t t _ m o c b t e d 0 b t u o d2 b t u o d 4 n a x ra d d v t s e t 2 e d o m 9 b t u o dr w p l t td n g l t t 5 c nb u s s s vc n 1 b t u o d3 b t u o d6 b t u o d 6 a d d vc nd d v 4 b t u o d5 b t u o dc n 7 b u s s s vs s vs s v b 0 c b rb 1 c b rr w p l t t 8 p b x ra s s va d d v 7 b t u o dr w p l t td n g l t t 9 n b x rc nd d v r w p g i dc nc n 0 1 s m tk c ti d t 0 a n i da c b tc n 1 1 s s vl e s k l ce t a r 4 a n i d2 a n i dd n g g i d 2 1 b u s s s vd d vb u s s s v 7 a n i d5 a n i d1 a n i d 3 1 e d o m ta d d va s s v d n g8 a n i d3 a n i d 4 1 s s v2 p a ca n e p lc nc nc n l c e p r w p b n e p lk l c f e rd n g9 b n i d6 b n i d3 b n i db c b td n g6 a n i d 5 1 1 p a ct e s e rc n l c e p r w p c n l c e p r w p c n l c e p r w p r w p g i do k l c t t s e t 1 e d o m 7 b n i d4 b n i d1 b n i dc n9 a n i d 6 1 r w pc nd n g l c e pp a x tn a x tn b x tp b x to d td n g l c e pd n g g i dd n g8 b n i d5 b n i d2 b n i d0 b n i dd n g note: nc used as test pins. do not connect.
18 dual gigabit ethernet device S2202 october 9, 2000 / revision c figure 10. S2202 pinout (top view) note: nc used as test pins. do not connect. t r p n m l k j h g f e d c b a d n g g i dd n g g i dr w p l t tr w p g i da 1 c b r6 a t u o d4 a t u o d2 a t u o dr w p l t t _ m o c a t e d r w p l t td n g l t td n g g i dr w p g i dr w pc n 1 d n g l t td n g l t t8 b t u o dc nr w p l t t7 a t u o d5 a t u o d9 a t u o d0 a t u o d8 a t u o dd n g l t td n g g i dr w p g i de d o m cr w p g i da s s v 2 2 b t u o d0 b t u o d _ m o c b t e d d n g l t td n g l t ta 0 c b rd n g l t t3 a t u o d1 a t u o dr w p l t td n g l t td n g g i d t s e t e d o m d n g g i ds r tp a x r 3 d n g l t tr w p l t t9 b t u o d t s e t 2 e d o m a d d vn a x r 4 6 b t u o d3 b t u o d1 b t u o d c nb u s s s vc n 5 c n5 b t u o d4 b t u o d d d vc na d d v 6 r w p l t tb 1 c b rb 0 c b r s s vs s vb u s s s v 7 d n g l t tr w p l t t7 b t u o d a d d va s s vp b x r 8 c nc nr w p g i d d d vc nn b x r 9 c na c b t0 a n i d i d tk c ts m t 0 1 d n g g i d2 a n i d4 a n i d e t a rl e s k l cs s v 1 1 1 a n i d5 a n i d7 a n i d b u s s s vd d vb u s s s v 2 1 3 a n i d8 a n i dd n g a s s va d d ve d o m t 3 1 6 a n i dd n gb c b t3 b n i d6 b n i d9 b n i dd n gk l c f e rb n e p l l c e p r w p c nc nc na n e p l2 p a cs s v 4 1 9 a n i dc n1 b n i d4 b n i d7 b n i d t s e t 1 e d o m o k l c tr w p g i d l c e p r w p c n l c e p r w p c n l c e p r w p c nt e s e r1 p a c 5 1 d n g0 b n i d2 b n i d5 b n i d8 b n i dd n gd n g g i dd n g l c e po d tp b x tn b x tn a x tp a x td n g l c e pc nr w p 6 1
19 S2202 dual gigabit ethernet device october 9, 2000 / revision c figure 11. compact 21mm x 21mm 156 tbga package thermal management device S2202 19.8?c/w q ja 3.5?c/w q jc
20 dual gigabit ethernet device S2202 october 9, 2000 / revision c tbcx dinx[0:9] t 1 t 2 serial data out figure 13. transmitter timing (tbc mode, tmode = 1) table 16. S2202 transmitter timing (tbc mode, tmode = 1) 1. all ac measurements are made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 c b t . t . r . w p u t e s a t a d0 . 1-s n. 1 e t o n e e s t 2 c b t . t . r . w d l o h a t a d5 . 0-s n d n a x c b t n e e w t e b t f i r d e s a h p k l c f e r 3 -3 +s n figure 12. transmitter timing (refclk mode, tmode = 0) table 15. S2202 transmitter timing (refclk mode, tmode = 0) 1. all ac measurements are made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). refclk dinx[0:9] t 1 t 2 serial data out s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c f e r . t . r . w p u t e s a t a d5 . 0-s n. 1 e t o n e e s t 2 k l c f e r . t . r . w d l o h a t a d5 . 1-s n
21 S2202 dual gigabit ethernet device october 9, 2000 / revision c table 17. S2202 receiver timing (full and half clock mode) 1. measurements made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0 v). 2. ttl/cmos ac timing measurements are assumed to have an output load of 10pf. s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 3 x 0 / 1 c b r . t . r . w p u t e s a t a d5 . 2s n s p b g 5 2 . 1 t a 2 , 1 1 = e d o m t t 4 x 0 / 1 c b r . t . r . w d l o h a t a d5 . 2s n1 = e d o m t t 5 x 0 / 1 c b r . t . r . w p u t e s a t a d5 . 2s n s p b g 5 2 . 1 t a 2 , 1 1 = e d o m t t 6 x 0 / 1 c b r . t . r . w d l o h a t a d5 . 2s n1 = e d o m t t 7 e s i r x 0 c b r o t e s i r x 1 c b r m o r f e m i t5 . 75 . 8s ns p b g 5 2 . 1 t a 2 , 1 t 1 r t , 1 f s e m i t l l a f d n a e s i r x 1 c b r4 . 2s n. 9 1 e r u g i f e e s . 2 e t o n e e s t 0 r t , 0 f s e m i t l l a f d n a e s i r x 0 c b r4 . 2s n. 9 1 e r u g i f e e s . 2 e t o n e e s t r d t , f d s e m i t l l a f d n a e s i r x t u o d4 . 2s n. 9 1 e r u g i f e e s . 2 e t o n e e s e l c y c y t u de l c y c y t u d x 0 / 1 c b r0 40 6% . 1 e t o n e e s table 18. receiver timing (external clock mode) 1. measurements made from the reference voltage levels of the clock (1.4v) to the valid input or output data levels (.8v or 2.0 v). s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 8 x t u o d o t a c b t y a l e d n o i t a g a p o r p 0 . 30 . 8s n e h t t a e c n a t i c a p a c d a o l f p 0 1 0 5 h c n i 3 a f o d n e w . e n i l n o i s s i m s n a r t
22 dual gigabit ethernet device S2202 october 9, 2000 / revision c figure 15. receiver timing (half clock mode, cmode = 0) figure 14. receiver timing (full clock mode, cmode = 1) rbc0x doutx[0:9], com_detx serial data in t 3 t 4 rbc1x rbc0x doutx[0:9], com_detx serial data in rbc1x t 5 t 6 t 7 t 5 t 6 doutx[0:9], com_detx serial data in t 8 tbca (input) figure 16. receiver timing (external clock mode) (tbca to data propagation delay, tmode = 0)
23 S2202 dual gigabit ethernet device october 9, 2000 / revision c note: measurements are made at 1.4v level of clocks. table 19. S2202 transmitter (tclko timing) figure 17. tclko timing refclk t 9 tclko s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 9 k l c f e r . t . r . w o k l c t0 . 15 . 6s n e l c y c y t u d o k l c t% 5 4% 5 5%
24 dual gigabit ethernet device S2202 october 9, 2000 / revision c r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w d d v n o e g a t l o v5 . 0 -0 . 5 +v n i p t u p n i l t t y n a n o e g a t l o v5 . 0 -7 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v0d d vv t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l c e p d e e p s h g i h5 2a m y t i v i t i s n e s d s e 1 v 0 0 5 r e v o r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c ? o t t c e p s e r h t i w n i p r e w o p y n a n o e g a t l o v s s v / d n g 3 1 . 33 . 37 4 . 3v n i p t u p n i l t t n o e g a t l o v07 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v d d v v 2 - d d vv s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t fe c n a r e l o t y c n e u q e r f0 0 1 -0 0 1 +m p p d t 2 - 1 y r t e m m y s0 40 6% . t p % 0 5 t a e l c y c y t u d t r c r t , f c r e m i t l l a f d n a e s i r k l c f e r2s n. % 0 8 - % 0 2 r e t t i j0 8s p n i a t n i a m o t , k a e p - o t - k a e p 3 . g n i n e p o e y e % 7 7 table 20. absolute maximum ratings table 21. recommended operating conditions table 22. reference clock requirements 1. human body model.
25 S2202 dual gigabit ethernet device october 9, 2000 / revision c s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h o ) l t t ( e g a t l o v h g i h t u p t u o4 . 28 . 2d d vv i n i m = d d v h o a m 4 - = v l o ) l t t ( e g a t l o v w o l t u p t u od n g5 2 0 .5 . 0v i n i m = d d v l o a m 4 = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2v v l i ) l t t ( e g a t l o v w o l t u p n id n g8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 4a v n i x a m = d d v , v 4 . 2 = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 6a v n i x a m = d d v , v 8 . = d d it n e r r u c y l p p u s0 7 50 6 6a mn r e t t a p 0 1 0 1 p d n o i t a p i s s i d r e w o p5 8 . 13 . 2w n r e t t a p 0 1 0 1 v f f i d g n i w s e g a t l o v t u p n i l a i t n e r e f f i d . n i m s t u p n i l c e p l a i t n e r e f f i d r o f 0 0 10 0 6 2v m. 1 2 e r u g i f e e s d v t u o e g a t l o v t u p t u o l a i r e s l a i t n e r e f f i d g n i w s 0 0 4 10 0 6 2v m. 0 2 e r u g i f e e s c n i e c n a t i c a p a c t u p n i3f p table 25. dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c r e t t i j l a t o tr e t t i j l a t o t t u p t u o a t a d l a i r e s2 9 1s p. k a e p - o t - k a e p t j d r e t t i j c i t s i n i m r e t e d t u p t u o a t a d l a i r e s0 8s p. k a e p - o t - k a e p t r s t , f s e m i t l l a f d n a e s i r t u p t u o a t a d l a i r e s0 0 3s p. 8 1 e r u g i f e e s . % 0 8 - % 0 2 s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c t k c o l ) y c n e u q e r f ( e m i t k c o l n o i t i s i u q c a y c n e u q e r f ) s p b g 5 2 . 1 ( ) k c o l f o s s o l ( 5 7 1s e l p m a s n r e t t a p e l d i b 0 1 / b 8 . p u t r a t s e c i v e d m o r f , s i s a b t j d e c n a r e l o t r e t t i j t u p n i c i t s i n i m r e t e d0 7 3s p r e t t i j t u p n i e c n a r e l o t e c n a r e l o t r e t t i j l a t o t t u p n i a t a d l a i r e s9 9 5s p y b d e i f i c e p s s a , k a e p - o t - k a e p . z 3 . 2 0 8 e e e i r r s r , f s e m i t l l a f d n a e s i r t u p n i a t a d l a i r e s0 3 3s p. 8 1 e r u g i f e e s . % 0 8 - % 0 2 table 23. serial data timing, transmit outputs table 24. serial data timing, receive inputs
26 dual gigabit ethernet device S2202 october 9, 2000 / revision c output load the S2202 serial outputs do not require output pulldown resistors. figure 21. high speed differential inputs figure 18. serial input/output rise and fall time figure 22. receiver input eye diagram jitter mask figure 19. ttl input/output rise and fall time figure 20. serial output load t r t f 80% 20% 50% 80% 20% 50% t r t f +2.0v +0.8v +2.0v +0.8v 0.01 f 0.01 f v dd -2.3v 100 0.01 f 0.01 f v dd - 1.3 v bit time amplitude 24%
27 S2202 dual gigabit ethernet device october 9, 2000 / revision c figure 23. loop filter capacitor connections cap1 270 22 nf cap2 270 S2202
28 dual gigabit ethernet device S2202 october 9, 2000 / revision c ordering information x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i - s2 0 2 2a g b t 6 5 1 C b t x xxxx x prefix device package amcc is a registered trademark of applied micro circuits corporation. copyright ? 1999 applied micro circuits corporation d106/r160 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (619) 450-9333 ? (800) 755-2622 ? fax: (619) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1

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